Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

摘要

This article presents two area/latency optimized gate level asynchronous fulladder designs which correspond to early output logic. The proposed full addersare constructed using the delay-insensitive dual-rail code and adhere to thefour-phase return-to-zero handshaking. For an asynchronous ripple carry adder(RCA) constructed using the proposed early output full adders, therelative-timing assumption becomes necessary and the inherent advantages of therelative-timed RCA are: (1) computation with valid inputs, i.e., forwardlatency is data-dependent, and (2) computation with spacer inputs involves abare minimum constant reverse latency of just one full adder delay, thusresulting in the optimal cycle time. With respect to different 32-bit RCAimplementations, and in comparison with the optimized strong-indication,weak-indication, and early output full adder designs, one of the proposed earlyoutput full adders achieves respective reductions in latency by 67.8, 12.3 and6.1 %, while the other proposed early output full adder achieves correspondingreductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty.Further, the proposed early output full adders based asynchronous RCAs enableminimum reductions in cycle time by 83.4, 15, and 8.8 % when consideringcarry-propagation over the entire RCA width of 32-bits, and maximum reductionsin cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typicalcarry chain length of 4 full adder stages, when compared to the least of thecycle time estimates of various strong-indication, weak-indication, and earlyoutput asynchronous RCAs of similar size. All the asynchronous full adders andRCAs were realized using standard cells in a semi-custom design fashion basedon a 32/28 nm CMOS process technology.